Carrier arrangement and method for processing a carrier by generating a crack structure
US10748801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.