Memory arrays and methods used in forming a memory array
US10748922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Nov 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.