Circuit and electronic device including an enhancement-mode transistor
US10749019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Jul 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device can include a channel layer and a barrier layer overlying the channel layer. In an embodiment, the electronic device can include a component disposed along a current path between a gate terminal and a gate electrode of a first transistor. In another embodiment, the electronic device can include a second transistor wherein source and gate electrodes of the second transistor are coupled to the gate electrode of the first transistor, and a drain electrode of the second transistor is coupled to the gate terminal. A circuit can include a transistor and a diode. The transistor can include a drain, a gate, and a source, wherein the drain is coupled to a drain terminal, and the source is coupled to a source terminal. The diode can have an anode is coupled to the gate terminal, and a cathode is coupled to a gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.