Transistor with a gate structure comprising a tapered upper surface
US10763176B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Oct 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.