Chip package assembly with composite stiffener
US10764996B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.