Method of reducing injection type of program disturb during program pre-charge in memory device
US10770157B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.