Fin-type FET with low source or drain contact resistance

US10777647B2 · kind B2 · utility

Assignee

• Elpis Technologies Inc. · CA

Inventors

• Kangguo Cheng · Schenectady, US
• Juntao Li · Cohoes, US
• Heng Wu · Guilderland, US
• Peng Xu · Guilderland, US

Key dates

• Filing date: May 22, 2019
• Grant date: Sep 15, 2020
• Expiry date: May 22, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.