Trench isolation preservation during transistor fabrication
US10784143B2 · kind B2 · utility
0Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.