Method to increase effective gate height
US10790148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2018 |
| Grant date | Sep 29, 2020 |
| Priority date | — |
| Expiry date | May 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.