Test structure leveraging the lowest metallization level of an interconnect structure

US10790204B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Mankyu Yang · Fishkill, US
• Vara Govindeswara Reddy Vakada · Beacon, US
• Edward P. Maciejewski · Wappingers Falls, US
• Brian J. Greene · Wappingers Falls, US
• Atsushi Ogino · Kodaira, JP
• Vikrant Chauhan · Beacon, US
• Prianka Sengupta · Malta, US

Key dates

• Filing date: Nov 9, 2018
• Grant date: Sep 29, 2020
• Expiry date: Jan 3, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.