Stacked channel structures for MOSFETs

US10790281B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Rishabh Mehandru · Portland, US
• Roza Kotlyar · Portland, US
• Stephen M. Cea · Hillsboro, US
• Patrick H. Keys · Portland, US

Key dates

• Filing date: Dec 3, 2015
• Grant date: Sep 29, 2020
• Expiry date: Dec 3, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.