Visualization of three-dimensional semiconductor structures
US10794839B2 · kind B2 · utility
3Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.