Multiple dies hardware processors and methods

US10795853B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nevine Nassif · Arlington, US
• Yen-Cheng Liu · Portland, US
• Krishnakanth V. Sistla · Beaverton, US
• Gerald Pasdast · San Jose, US
• Siva Soumya Eachempati · Campbell, US
• Tejpal Singh · Santa Clarita, US
• Ankush Varma · Portland, US
• Mahesh Kumashikar · Kanchinakote, IN
• Srikanth Nimmagadda · Kanchinakote, IN
• Carleton L. Molnar · Northborough, US
• Vedaraman Geetha · Fremont, US
• Jeffrey D. Chamberlain · Tracy, US
• William R. Halleck · Lancaster, US
• George Z. Chrysos · Milford, US
• John R. Ayers · Portland, US
• Dheeraj Subbareddy · Santa Clara, US

Key dates

• Filing date: Sep 30, 2017
• Grant date: Oct 6, 2020
• Expiry date: Apr 9, 2039

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.