Test structures connected with the lowest metallization levels in an interconnect structure

US10796973B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Mankyu Yang · Fishkill, US
• Vara Govindeswara Reddy Vakada · Beacon, US
• Edward P. Maciejewski · Wappingers Falls, US
• Brian J. Greene · Wappingers Falls, US
• Atsushi Ogino · Kodaira, JP
• Vikrant Chauhan · Beacon, US
• Prianka Sengupta · Malta, US

Key dates

• Filing date: May 29, 2019
• Grant date: Oct 6, 2020
• Expiry date: May 29, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.