Leakage control for gate-all-around field-effect transistor devices
US10797163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Oct 6, 2020 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are provided to fabricate embedded insulating layers within an active semiconductor layer of substrate to reduce leakage between field-effect transistor devices and the semiconductor substrate. For example, an epitaxial semiconductor layer is formed on a surface of a semiconductor substrate. An ion implantation process is performed to form an embedded insulation layer within the semiconductor substrate below the epitaxial semiconductor layer. A nanosheet field-effect transistor device is formed over the embedded insulation layer. The nanosheet field-effect transistor device includes active nanosheet channel layers, source/drain layers, and a high-k dielectric/metal gate structure formed around the active nanosheet channel layers. The process of forming the nanosheet field-effect transistor device includes removing the epitaxial semiconductor layer to release the active nanosheet channel layers. The embedded insulation layer isolates the high-k dielectric/metal gate structure and the source/drain layers from the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.