Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes
US10802077B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.