Porous silicon relaxation medium for dislocation free CMOS devices
US10804166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2019 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.