High density embedded interconnects in substrate
US10804195B2 · kind B2 · utility
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24Claims
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Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.