Self-aligned chamferless interconnect structures of semiconductor devices
US10804199B2 · kind B2 · utility
2Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Oct 13, 2020 |
| Priority date | — |
| Expiry date | Sep 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.