Semiconductor device having two-part spacer

US10804368B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruqiang Bao · Niskayuna, US
• Junli Wang · Slingerlands, US
• Dechao Guo · Niskayuna, US
• Heng Wu · Guilderland, US
• Ernest Y. Wu · South Burlington, US

Key dates

• Filing date: Jul 30, 2018
• Grant date: Oct 13, 2020
• Expiry date: Jul 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.