Memory device selectively correcting an error in data during a read operation, memory system including the same, and operating method of memory system
US10810080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Oct 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes an error correction code (“ECC”) generation circuit using write data to generate an ECC to be stored together with the write data; a memory device, during a write operation, storing received data and a received ECC in a memory core, and, during a read operation, checking for an error in data read from the memory core, correcting the error in read data using the ECC and outputting error-corrected data and the ECC, when the error in the read data is between one bit and N bits inclusive, and outputting the read data and the ECC when no error is present in the read data or the error in the read data exceeds N bits; and an error correction circuit correcting, when an error is present in data outputted from the memory device, the error in the data outputted using an ECC outputted from the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.