Stacked semiconductor devices having dissimilar-sized dies
US10818570B1 · kind B1 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | May 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06568
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device is provided, which includes a first die, a second die and a heat dissipating layer. The first die has a pre-determined size. The second die is bonded to the first die using a dielectric material, wherein the second die is smaller than the first die. The heat dissipating layer is surrounding the second die, wherein the heat dissipating layer has an outer dimension that is equal to the size of the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.