Method for fabricating a field-effect transistor
US10818775B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Nov 14, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.