Semiconductor structure and method for preparing the same
US10818800B2 · kind B2 · utility
3Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/611
Abstract
The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.