Gate cut first isolation formation with contact forming process mask protection
US10825811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Feb 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.