Semiconductor layout structure including asymmetrical channel region
US10825898B2 · kind B2 · utility
1Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Nov 3, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.