Coherent cache with simultaneous data requests in same addressable index
US10831661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | May 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.