Gate contact over active region with self-aligned source/drain contact
US10832943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure is provided. The method includes depositing a dielectric material in a first opening above a first source/drain region in a first region of the semiconductor structure and in a second and a third opening above a respective second and a third source/drain region in a second region of the silicon structure. There is a gate region between the second and third source/drain regions. The method etches away the dielectric material deposited in the first opening and deposits an organic material in the first opening. The method further etches a region above the gate region between the second and third source/drain regions to expose the gate region and form a fourth opening and removes the organic material from the first opening. The method deposits a metal in the first opening and the fourth opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.