Methods and structures for a gate cut
US10832966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
Abstract
Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.