Fabricating tapered semiconductor devices
US10832971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.