Field-effect transistors with self-aligned and non-self-aligned contact openings
US10833160B1 · kind B1 · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Apr 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.