Bitline boost for nonvolatile memory
US10839915B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology and structure for a bit line boost during a programming operation in a nonvolatile memory are described. The inhibit bit line is driven for a first precharge time period with a constant current. The program bit line boost is delayed for a second precharge time period while continuing to drive the inhibit bit line to account for a resistance-capacitance (RC) delay on the inhibit bit line. Thereafter, the program bit line is boosted at the end of the second time period to a program voltage level. The signal level at the fare end of the bit line remote from the driven end of the bit line is sensed to determine when the inhibit bit line reaches a level (e.g. VDDSA) or a level at which the current limits are turned off. Thereafter, the bit line boost can be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.