Patent · US Active

Redundancy circuitry for memory application

US10839934B2 · kind B2 · utility

0Cited by

6References

21Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Rahul Mathur · Austin, US
Andy Wangkun Chen · Austin, US
Gaurang Prabhakar Narvekar · San Jose, US
Sanjay Mangal · Austin, US
Yew Keong Chong · Austin, US
Bikas Maiti · Austin, US
Martin Jay Kinkade · Austin, US

Key dates

Filing date	May 30, 2018
Grant date	Nov 17, 2020
Priority date	—
Expiry date	Sep 21, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/816
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.