Patent · US Active

Stacked silicon package assembly having enhanced stiffener

US10840192B1 · kind B1 · utility

1Cited by

8References

21Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Nael Zohni · Campbell, US
Shin S. Low · Cupertino, US
Inderjit Singh · Saratoga, US
Raghunandan Chaware · Mountain View, US
Ganesh Hariharan · Milpitas, US

Key dates

Filing date	Apr 6, 2017
Grant date	Nov 17, 2020
Priority date	—
Expiry date	May 31, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/35121
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip package assembly and method for fabricating the same are provided which utilize a stiffener to improve a package substrate against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die and a stiffener. The package substrate has a first surface and a second surface coupled by a side wall. The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface bonded to at least one of the first and second surfaces of the package substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.