Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
US10840229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Nov 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.