High-density low voltage non-volatile differential memory bit-cell with shared plate line
US10847201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.