Multi-chip semiconductor package
US10847505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Sep 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.