Layout pattern of a static random access memory

US10847521B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chun-Hsien Huang · Jiali, TW
• Ching-Cheng Lung · Tainan, TW
• Yu-Tse Kuo · Tainan, TW
• Shu-Ru Wang · Taichung, TW
• Chun-Yen Tseng · Tainan, TW

Key dates

• Filing date: Oct 5, 2018
• Grant date: Nov 24, 2020
• Expiry date: Nov 10, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL1) and a gate of a first pull-down device (PD1). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL2) and a gate of a second pull-down device (PD2) and the gate of the PD1 is directly under the gate of the PD2.