Ternary content addressable memory unit capable of reducing charge sharing effect
US10861549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Jul 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.