Platform and method of operating for integrated end-to-end CMP-less interconnect process
US10861744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.