Non-volatile memory cells with floating gates in dedicated trenches
US10879252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Dec 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.