Memory device, memory system including the same and operation method of the memory system
US10884848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: an in-memory error correction code generating circuit suitable for generating an in-memory error correction code based on a data received from a memory controller during a write operation; a memory core suitable for storing the received data and the in-memory error correction code during the write operation; an in-memory error correction circuit suitable for correcting an error of the data which is read from the memory core based on the in-memory error correction code which is read from the memory core during a read operation; and a data transmitter suitable for transferring the data whose error is corrected by the in-memory error correction circuit to the memory controller during the read operation, and transferring the data which is read from the memory core to the memory controller during a read retry operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.