Results processing circuits and methods associated with computational memory cells
US10891076B1 · kind B1 · utility
13Cited by
272References
44Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 4, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Oct 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.