Semiconductor devices having discretely located passivation material, and associated systems and methods
US10896886B2 · kind B2 · utility
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2References
27Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Jan 19, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01029
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.