Memory system and operating method thereof
US10901842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2019 |
| Grant date | Jan 26, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/098
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code based on write data, and generate a second system error correction code based on the write data and the first system error correction code; and a memory including: a memory error correction code generation circuit configured to generate a memory error correction code based on the write data and the first system error correction code transferred from the memory controller; and a memory core configured to store the write data, the first system error correction code, the second system error correction code and the memory error correction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.