Memory circuit
US10910040B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.