Using loop exit prediction to accelerate or suppress loop mode of a processor
US10915322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2018 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Nov 28, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.