Memory system and operating method thereof
US10915398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.