Methods of forming metal silicide layers and metal silicide layers formed therefrom
US10916433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Mar 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.