Three-dimensional memory device including electrically conductive layers with molybdenum-containing liners
US10916504B2 · kind B2 · utility
4Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.